Mitsuru Shiozaki
Mitsuru Shiozaki
Verified email at fc.ritsumei.ac.jp
Title
Cited by
Cited by
Year
On measurable side-channel leaks inside ASIC design primitives
T Sugawara, D Suzuki, M Saeki, M Shiozaki, T Fujino
International Conference on Cryptographic Hardware and Embedded Systems, 159-178, 2013
392013
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with delay-time measurement
K Fruhashi, M Shiozaki, A Fukushima, T Murayama, T Fujino
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2325-2328, 2011
372011
Reversing stealthy dopant-level circuits
T Sugawara, D Suzuki, R Fujii, S Tawa, R Hori, M Shiozaki, T Fujino
International Workshop on Cryptographic Hardware and Embedded Systems, 112-126, 2014
362014
Diffusion Programmable Device: The device to prevent reverse engineering.
M Shiozaki, R Hori, T Fujino
IACR Cryptol. ePrint Arch. 2014, 109, 2014
212014
A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications
M Taniguchi, M Shiozaki, H Kubo, T Fujino
2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE), 525-527, 2013
142013
Signal distribution architecture and semiconductor device
H Ikeda, M Sasaki, A Iwata, M Shiozaki, A Mori
US Patent 7,538,603, 2009
132009
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM
M Shiozaki, T Kubota, T Nakai, A Takeuchi, T Nishimura, T Fujino
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1462-1465, 2015
122015
12GHz low-area-overhead standing-wave clock distribution with inductively-loaded and coupled technique
M Sasaki, M Shiozaki, A Mori, A Iwata, H Ikeda
2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007
112007
Reversing stealthy dopant-level circuits
T Sugawara, D Suzuki, R Fujii, S Tawa, R Hori, M Shiozaki, T Fujino
Journal of Cryptographic Engineering 5 (2), 85-94, 2015
102015
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks
T Nakai, M Shibatani, M Shiozaki, T Kubota, T Fujino
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2547-2550, 2014
102014
17GHz fine grid clock distribution with uniform-amplitude standing-wave oscillator
M Sasaki, M Shiozaki, A Mori, A Iwata, H Ikeda
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 98-99, 2006
82006
LSI Implementation Method of DES Cryptographic Circuit Utilizing Domino-RSL Gate Resistant to DPA Attack
K Kojima
SASIMI2010, 196-201, 2010
72010
VLSI Design and Test for Systems Dependability
S Asai
Springer, 2018
52018
On measurable side-channel leaks inside ASIC design primitives
T Sugawara, D Suzuki, M Saeki, M Shiozaki, T Fujino
Journal of Cryptographic Engineering 4 (1), 59-73, 2014
52014
Evaluation of on-chip decoupling capacitor’s effect on AES cryptographic circuit
T Nakai, M Shiozaki, T Kubota, T Fujino
Synthesis And System Integration of Mixed Information Technologies 13, 2013
52013
PowerAnalysis resistant IP core using IO-masked dual-rail ROM for easy implementation into low-power area-efficient cryptographic LSIs
M Shibatani, M Shiozaki, Y Hashimoto, T Kubota, T Fujino
Synthesis and System Integration of Mixed Information Technologies, 82-87, 2013
52013
20GHz uniform-phase uniform-amplitude standing-wave clock distribution
M Shiozaki, M Sasaki, A Mori, A Iwata, H Ikeda
IEICE Electronics Express 3 (2), 11-16, 2006
52006
Deep learning side-channel attack against hardware implementations of AES
T Kubota, K Yoshida, M Shiozaki, T Fujino
Microprocessors and Microsystems, 103383, 2020
42020
Model-extraction attack against FPGA-DNN accelerator utilizing correlation electromagnetic analysis
K Yoshida, T Kubota, M Shiozaki, T Fujino
2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019
42019
Tamper-resistant cryptographic hardware
T Fujino, T Kubota, M Shiozaki
IEICE Electronics Express 14 (2), 20162004-20162004, 2017
42017
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