Rafael Asenjo Plaza
Rafael Asenjo Plaza
Full Professor. Universidad de Málaga
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Cited by
Cited by
Analytical modeling of pipeline parallelism
A Navarro, R Asenjo, S Tabik, C Cascaval
2009 18th International Conference on Parallel Architectures and Compilation …, 2009
Pro TBB: C++ Parallel Programming with Threading Building Blocks
M Voss, R Asenjo, J Reinders
Apress, 2019
Adaptive Partitioning for Irregular Applications on Heterogeneous CPU-GPU Chips
A Vilches, R Asenjo, A Navarro, F Corbera, R Gran, M Garzarán
Procedia Computer Science 51, 140-149, 2015
Heterogeneous parallel_for Template for CPU–GPU Chips
A Navarro, F Corbera, A Rodriguez, A Vilches, R Asenjo
International Journal of Parallel Programming 47 (2), 213-233, 2019
Load balancing using work-stealing for pipeline parallelism in emerging applications
A Navarro, R Asenjo, S Tabik, C Caşcaval
Proceedings of the 23rd international conference on Supercomputing, 517-518, 2009
Strategies for maximizing utilization on multi-CPU and multi-GPU heterogeneous architectures
A Navarro, A Vilches, F Corbera, R Asenjo
The Journal of Supercomputing 70 (2), 756-771, 2014
Mapping streaming applications on commodity multi-CPU and GPU on-chip processors
A Vilches, A Navarro, R Asenjo, F Corbera, R Gran, MJ Garzaran
IEEE Transactions on Parallel and Distributed Systems 27 (4), 1099-1115, 2016
Automatic parallelization of irregular applications
E Gutiérrez, R Asenjo, O Plata, EL Zapata
Parallel Computing 26 (13-14), 1709-1738, 2000
Sparse block and cyclic data distributions for matrix computations
R Asenjo, LF Romero, M Ujaldon, EL Zapata
Advances in Parallel Computing 10, 359-377, 1995
On parallel branch and bound frameworks for global optimization
JFR Herrera, JMG Salmerón, EMT Hendrix, R Asenjo, LG Casado
Journal of Global Optimization 69 (3), 547-560, 2017
Simultaneous multiprocessing in a software-defined heterogeneous FPGA
J Nunez-Yanez, S Amiri, M Hosseinabady, A Rodríguez, R Asenjo, ...
The Journal of Supercomputing 75 (8), 4078-4095, 2019
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs
A Rodríguez, A Navarro, R Asenjo, F Corbera, R Gran, D Suárez, ...
Journal of Systems Architecture 98, 27-40, 2019
ClinicAppChain: A Low-Cost Blockchain Hyperledger Solution for Healthcare
DJ Munoz, DA Constantinescu, R Asenjo, L Fuentes
International Congress on Blockchain and Applications, 36-44, 2019
Efficiency and productivity for decision making on low-power heterogeneous CPU+ GPU SoCs
DA Constantinescu, A Navarro, F Corbera, JA Fernández-Madrigal, ...
The Journal of Supercomputing 77 (1), 44-65, 2021
Global data-reallocation via communication aggregation in Chapel
A Sanz, R Asenjo, J López, R Larrosa, A Navarro, V Litvinov, SE Choi, ...
24th International Symposium on Computer Architecture and High Performance …, 2012
On the automatic parallelization of sparse and irregular fortran codes
R Asenjo, E Gutierrez, Y Lin, D Padua, B Pottengerg, E Zapata
Technical Report 1512, University of Illinois at Urbana-Champaign, CSRD, 1996
New shape analysis techniques for automatic parallelization of C codes
F Corbera, R Asenjo, EL Zapata
Proceedings of the 13th international conference on Supercomputing, 220-227, 1999
A framework to capture dynamic data structures in pointer-based codes
F Corbera, R Asenjo, EL Zapata
IEEE Transactions on Parallel and Distributed Systems 15 (2), 151-166, 2004
High-level template for the task-based parallel wavefront pattern
AJ Dios, R Asenjo, A Navarro, F Corbera, EL Zapata
2011 18th International Conference on High Performance Computing, 1-10, 2011
Parallelizing irregular C codes assisted by interprocedural shape analysis
R Asenjo, R Castillo, F Corbera, A Navarro, A Tineo, EL Zapata
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-12, 2008
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