Cnvlutin: Ineffectual-neuron-free deep neural network computing J Albericio, P Judd, T Hetherington, T Aamodt, NE Jerger, A Moshovos ACM SIGARCH Computer Architecture News 44 (3), 1-13, 2016 | 473 | 2016 |
Stripes: Bit-serial deep neural network computing P Judd, J Albericio, T Hetherington, TM Aamodt, A Moshovos 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 254 | 2016 |
Bit-pragmatic deep neural network computing J Albericio, A Delmás, P Judd, S Sharify, G O'Leary, R Genov, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 119 | 2017 |
Doppelgänger: a cache for approximate computing JS Miguel, J Albericio, A Moshovos, NE Jerger Proceedings of the 48th International Symposium on Microarchitecture, 50-61, 2015 | 103 | 2015 |
Reduced-precision strategies for bounded memory in deep neural nets P Judd, J Albericio, T Hetherington, T Aamodt, NE Jerger, R Urtasun, ... arXiv preprint arXiv:1511.05236, 2015 | 88 | 2015 |
Proteus: Exploiting numerical precision variability in deep neural networks P Judd, J Albericio, T Hetherington, TM Aamodt, NE Jerger, A Moshovos Proceedings of the 2016 International Conference on Supercomputing, 1-12, 2016 | 77 | 2016 |
The reuse cache: downsizing the shared last-level cache J Albericio, P Ibáñez, V Viñals, JM Llabería 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013 | 52 | 2013 |
The bunker cache for spatio-value approximation J San Miguel, J Albericio, NE Jerger, A Jaleel 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 45 | 2016 |
The inner most loop iteration counter: a new dimension in branch history A Seznec, J San Miguel, J Albericio 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture …, 2015 | 25* | 2015 |
Exploiting reuse locality on inclusive shared last-level caches J Albericio, P Ibáñez, V Viñals, JM Llabería ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-19, 2013 | 22 | 2013 |
Wormhole: Wisely predicting multidimensional branches J Albericio, J San Miguel, NE Jerger, A Moshovos 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 509-520, 2014 | 14 | 2014 |
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache J Albericio, R Gran, P Ibánez, V Viñals, JM Llabería ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-20, 2012 | 14 | 2012 |
Proteus: Exploiting precision variability in deep neural networks P Judd, J Albericio, T Hetherington, T Aamodt, NE Jerger, R Urtasun, ... Parallel Computing 73, 40-51, 2018 | 9 | 2018 |
Evaluating the memory system behavior of smartphone workloads G Narancic, P Judd, D Wu, I Atta, M Elnacouzi, J Zebchuk, J Albericio, ... 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 8 | 2014 |
Value-Based Deep-Learning Acceleration A Moshovos, J Albericio, P Judd, AD Lascorz, S Sharify, T Hetherington, ... IEEE Micro 38 (1), 41-55, 2018 | 6 | 2018 |
Wormhole branch prediction using multidimensional histories J Albericio, J San Miguel, NE Jerger, A Moshovos JWAC-4: Championship Branch Prediction, 2014 | 4 | 2014 |
Exploiting Typical Values to Accelerate Deep Learning A Moshovos, J Albericio, P Judd, AD Lascorz, S Sharify, Z Poulos, ... Computer 51 (5), 18-30, 2018 | 3 | 2018 |
Practical multidimensional branch prediction A Seznec, J San Miguel, J Albericio IEEE Micro 36 (3), 10-19, 2016 | 3 | 2016 |
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs M Ortín, A Ferrerón, J Albericio, D Suárez, M Villarroya-Gaudó, C Izu, ... Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi …, 2013 | 2 | 2013 |
Tensordash: Exploiting sparsity to accelerate deep neural network training M Mahmoud, I Edo, AH Zadeh, OM Awad, G Pekhimenko, J Albericio, ... 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 1 | 2020 |