Stuart Biles
Stuart Biles
Fellow, ARM
確認したメール アドレス: arm.com
タイトル
引用先
引用先
Managing cache coherency in a data processing apparatus
E Özer, SD Biles, SA Ford
US Patent 7,937,535, 2011
3072011
An architecture framework for transparent instruction set customization in embedded processors
N Clark, J Blome, M Chu, S Mahlke, S Biles, K Flautner
32nd International Symposium on Computer Architecture (ISCA'05), 272-283, 2005
1902005
The ARM scalable vector extension
N Stephens, S Biles, M Boettcher, J Eapen, M Eyole, G Gabrielli, ...
IEEE Micro 37 (2), 26-39, 2017
1092017
Handling access requests in a data processing apparatus
DH Mansell, SD Biles, SJ Hill
US Patent 7,657,694, 2010
852010
Contention management for a hardware transactional memory
G Blake, TN Mudge, SD Biles, NYS Chong, E Ozer, RG Dreslinski
US Patent App. 12/292,565, 2009
722009
Cache miss detection in a data processing apparatus
M Ghosh, E Özer, SD Biles
US Patent 8,099,556, 2012
712012
Multiple thread instruction fetch from different cache levels
E Özer, SD Biles
US Patent 7,769,955, 2010
712010
Cache management within a data processing apparatus
SD Biles, RR Grisenthwaite, DH Mansell
US Patent 8,041,897, 2011
662011
Contention management for a hardware transactional memory
SD Biles, G Blake, TN Mudge
US Patent 9,513,959, 2016
642016
Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion
JFM Pruvost, NBE Lataille, SD Biles
US Patent 7,162,590, 2007
622007
Apparatus and method for loading data values
SD Biles, CB Dornan, V Vasekin, AC Rose
US Patent 7,111,126, 2006
472006
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches
M Ghosh, E Ozer, S Ford, S Biles, HHS Lee
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
462009
Efficiency of cache memory operations
SD Biles, NC Paver, C Sudanthi, TC Mace
US Patent 8,001,331, 2011
452011
Reuseable configuration data
SD Biles, K Flautner, S Mahlke, N Clark
US Patent 7,318,143, 2008
432008
Data processing apparatus and method for controlling access to secure memory by virtual machines executing on processing circuirty
DH Mansell, RR Grisenthwaite, SD Biles
US Patent 8,418,175, 2013
382013
Data processing apparatus and method for handling corrupted data values
SD Biles
US Patent 7,269,759, 2007
382007
Program subgraph identification
SD Biles, K Flautner, S Mahlke, N Clark
US Patent 7,343,482, 2008
372008
Handling of write access requests to shared memory in a data processing apparatus
FCM Piry, PJ Raphalen, NBE Lataille, SD Biles, RR Grisenthwaite
US Patent 8,271,730, 2012
362012
Two-level branch prediction apparatus
SD Biles
US Patent 7,831,817, 2010
332010
Data processing apparatus and method for managing multiple program threads executed by processing circuitry
E Özer, SD Biles
US Patent 8,205,206, 2012
322012
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