Javier Navaridas
Javier Navaridas
School of Computer Science, The University of Manchester
確認したメール アドレス: manchester.ac.uk
Understanding the interconnection network of SpiNNaker
J Navaridas, M Luján, J Miguel-Alonso, LA Plana, S Furber
Proceedings of the 23rd international conference on Supercomputing, 286-295, 2009
An empirical evaluation of high-level synthesis languages and tools for database acceleration
O Arcas-Abella, G Ndu, N Sonmez, M Ghasempour, A Armejach, ...
2014 24th International Conference on Field Programmable Logic and …, 2014
Twisted torus topologies for enhanced interconnection networks
JM Camara, M Moreto, E Vallejo, R Beivide, J Miguel-Alonso, C Martinez, ...
IEEE Transactions on Parallel and Distributed Systems 21 (12), 1765-1778, 2010
Simulating and evaluating interconnection networks with INSEE
J Navaridas, J Miguel-Alonso, JA Pascual, FJ Ridruejo
Simulation Modelling Practice and Theory 19 (1), 494-515, 2011
A survey on optical network-on-chip architectures
S Werner, J Navaridas, M Luján
ACM Computing Surveys (CSUR) 50 (6), 1-37, 2017
The exanest project: Interconnects, storage, and packaging for exascale systems
M Katevenis, N Chrysos, M Marazakis, I Mavroidis, F Chaix, N Kallimanis, ...
2016 Euromicro Conference on Digital System Design (DSD), 60-67, 2016
Effects of topology-aware allocation policies on scheduling performance
JA Pascual, J Navaridas, J Miguel-Alonso
Workshop on Job Scheduling Strategies for Parallel Processing, 138-156, 2009
Reducing complexity in tree-like computer interconnection networks
J Navaridas, J Miguel-Alonso, FJ Ridruejo, W Denzel
Parallel computing 36 (2-3), 71-85, 2010
Interconnection network simulation using traces of MPI applications
J Miguel-Alonso, J Navaridas, FJ Ridruejo
International Journal of Parallel Programming 37 (2), 153-174, 2009
A survey on design approaches to circumvent permanent faults in networks-on-chip
S Werner, J Navaridas, M Luján
ACM Computing Surveys (CSUR) 48 (4), 1-36, 2016
Designing low-power, low-latency networks-on-chip by optimally combining electrical and optical links
S Werner, J Navaridas, M Luján
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
Effects of job and task placement on parallel scientific applications performance
J Navaridas, JA Pascual, J Miguel-Alonso
2009 17th Euromicro International Conference on Parallel, Distributed and …, 2009
Amon: An advanced mesh-like optical noc
S Werner, J Navaridas, M Luján
2015 IEEE 23rd Annual Symposium on High-Performance Interconnects, 52-59, 2015
Mixed-radix twisted torus interconnection networks
JM Cámara, M Moretó, E Vallejo, R Beivide, J Miguel-Alonso, C Martinez, ...
2007 IEEE International Parallel and Distributed Processing Symposium, 1-10, 2007
Population-based routing in the SpiNNaker neuromorphic architecture
S Davies, J Navaridas, F Galluppi, S Furber
The 2012 International Joint Conference on Neural Networks (IJCNN), 1-8, 2012
Scalable communications for a million-core neural processing architecture
C Patterson, J Garside, E Painkras, S Temple, LA Plana, J Navaridas, ...
Journal of Parallel and Distributed Computing 72 (11), 1507-1520, 2012
CHO: towards a benchmark suite for OpenCL FPGA accelerators
G Ndu, J Navaridas, M Luján
Proceedings of the 3rd International Workshop on OpenCL, 1-10, 2015
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric
MM Khan, AD Rast, J Navaridas, X Jin, LA Plana, M Luján, S Temple, ...
Parallel Computing 37 (8), 392-409, 2011
On synthesizing workloads emulating MPI applications
J Navaridas, J Miguel-Alonso, FJ Ridruejo
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-8, 2008
The next generation of Exascale-class systems: the ExaNeSt project
R Ammendola, A Biagioni, P Cretaro, O Frezza, FL Cicero, A Lonardo, ...
2017 Euromicro Conference on Digital System Design (DSD), 510-515, 2017
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