| Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs Y Omura, S Horiguchi, M Tabe, K Kishi IEEE Electron Device Letters 14 (12), 569-571, 1993 | 321 | 1993 |
| 0.1-mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer Y Omura, S Nakashima, K Izumi, T Ishii IEEE transactions on electron devices 40 (5), 1019-1022, 1993 | 137 | 1993 |
| Method of manufacturing SOI semiconductor element Y Omura, Y Kunii, K Izumi US Patent 5,188,973, 1993 | 92 | 1993 |
| 50-nm channel nMOSFET/SIMOX with an ultrathin 2-or 6-nm thick silicon layer and their significant features of operations Y Omura, K Kurihara, Y Takahashi, T Ishiyama, Y Nakajima, K Izumi IEEE Electron Device Letters 18 (5), 190-193, 1997 | 76 | 1997 |
| Low-power 1/2 frequency dividers using 0.1-mu m CMOS circuits built with ultrathin SIMOX substrates M Fujishima, K Asada, Y Omura, K Izumi IEEE journal of solid-state circuits 28 (4), 510-512, 1993 | 59 | 1993 |
| SIMOX technology and its application to CMOS LSIs K Izumi, Y Ōmura, T Sakai Journal of electronic materials 12, 845-861, 1983 | 55 | 1983 |
| A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter Y Kado, M Suzuki, K Koike, Y Omura, K Izumi IEICE transactions on electronics 76 (5), 853-857, 1993 | 54 | 1993 |
| Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime SI Yanagi, A Nakakubo, Y Omura IEEE Electron Device Letters 22 (6), 278-280, 2001 | 46 | 2001 |
| A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer K Ohwada, Y Omura, E Sano IEEE Transactions on Electron Devices 28 (9), 1084-1087, 1981 | 39 | 1981 |
| Physical basis and limitation of universal mobility behavior in fully depleted silicon-on-insulator Si inversion layers M Shoji, Y Omura, M Tomizawa Journal of applied physics 81 (2), 786-794, 1997 | 34 | 1997 |
| A lateral, unidirectional, bipolar‐type insulated‐gate transistor—A novel semiconductor device Y Ōmura Applied Physics Letters 40 (6), 528-529, 1982 | 34 | 1982 |
| Simplified analysis of body-contact effect for MOSFET/SOI Y Omura, K Izumi IEEE transactions on electron devices 35 (8), 1391-1393, 1988 | 33 | 1988 |
| Temperature dependence of analog performance, linearity, and harmonic distortion for a ge-source tunnel FET E Datta, A Chattopadhyay, A Mallik, Y Omura IEEE Transactions on Electron Devices 67 (3), 810-815, 2020 | 32 | 2020 |
| Quantum mechanical transport characteristics in ultimately miniaturized MOSFETs/SIMOX Y Omura, T Ishiyama, M Shoji, K Izumi Proceedings of the 10th International Symposium on SOI Technology and …, 1996 | 32 | 1996 |
| MOS Devices for Low-voltage and Low-energy Applications Y Omura, A Mallik, N Matsuo John Wiley & Sons, 2017 | 31 | 2017 |
| Impact of fin aspect ratio on short-channel control and drivability of multiple-gate SOI MOSFET's Y Omura, H Konishi, K Yoshimoto JSTS: Journal of Semiconductor Technology and Science 8 (4), 302-310, 2008 | 31 | 2008 |
| Quantum mechanical influences on short-channel effects in ultra-thin MOSFET/SIMOX devices Y Omura, K Izumi IEEE Electron Device Letters 17 (6), 300-302, 1996 | 30 | 1996 |
| Detailed investigation of geometrical factor for pseudo-MOS transistor technique K Komiya, N Bresson, S Sato, S Cristoloveanu, Y Omura IEEE transactions on electron devices 52 (3), 406-412, 2005 | 29 | 2005 |
| Physical background of substrate current characteristics and hot-carrier immunity in short-channel ultrathin-film MOSFET's/SIMOX Y Omura, K Izumi IEEE transactions on electron devices 41 (3), 352-358, 1994 | 29 | 1994 |
| Subfemtojoule deep submicrometer-gate CMOS built in ultra-thin Si film on SIMOX substrates H Miki, T Ohmameuda, M Kumon, K Asada, T Sugano, Y Omura, K Izumi, ... IEEE transactions on electron devices 38 (2), 373-377, 1991 | 29 | 1991 |
Shingo SatoKansai UniversityVerified email at kansai-u.ac.jp
