| AutoBridge: Coupling coarse-grained floorplanning and pipelining for high-frequency HLS design on multi-die FPGAs L Guo, Y Chi, J Wang, J Lau, W Qiao, E Ustun, Z Zhang, J Cong The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays …, 2021 | 84* | 2021 |
| FPGA HLS today: successes, challenges, and opportunities J Cong, J Lau, G Liu, S Neuendorffer, P Pan, K Vissers, Z Zhang ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15 (4), 1-42, 2022 | 76 | 2022 |
| Hardware acceleration of long read pairwise overlapping in genome sequencing: A race between fpga and gpu L Guo*, J Lau*, Z Ruan, P Wei, J Cong 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019 | 76 | 2019 |
| Sextans: A streaming accelerator for general-purpose sparse-matrix dense-matrix multiplication L Song, Y Chi, A Sohrabizadeh, Y Choi, J Lau, J Cong Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | 53* | 2022 |
| Extending high-level synthesis for task-parallel programs Y Chi, L Guo, J Lau, Y Choi, J Wang, J Cong 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021 | 47 | 2021 |
| Analysis and optimization of the implicit broadcasts in FPGA HLS to improve maximum frequency L Guo*, J Lau*, Y Chi, J Wang, CH Yu, Z Chen, Z Zhang, J Cong 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 35* | 2020 |
| CHARM: Composing heterogeneous accelerators for matrix multiply on Versal ACAP architecture J Zhuang, J Lau, H Ye, Z Yang, Y Du, J Lo, K Denolf, S Neuendorffer, ... Proceedings of the 2023 ACM/SIGDA International Symposium on Field …, 2023 | 21 | 2023 |
| HeteroRefactor: Refactoring for heterogeneous computing with FPGA J Lau*, A Sivaraman*, Q Zhang*, MA Gulzar, J Cong, M Kim 2020 IEEE/ACM 42nd International Conference on Software Engineering (ICSE …, 2020 | 18 | 2020 |
| TAPA: A scalable task-parallel dataflow programming framework for modern FPGAs with co-optimization of HLS and physical design L Guo*, Y Chi*, J Lau*, L Song, X Tian, M Khatti, W Qiao, J Wang, E Ustun, ... ACM Transactions on Reconfigurable Technology and Systems 16 (4), 2023 | 5 | 2023 |
| RapidStream 2.0: Automated parallel implementation of latency insensitive FPGA designs through partial reconfiguration L Guo, P Maidee, Y Zhou, C Lavin, E Hung, W Li, J Lau, W Qiao, Y Chi, ... ACM Transactions on Reconfigurable Technology and Systems, 2023 | 3 | 2023 |
| TARO: Automatic optimization for free-running kernels in FPGA high-level synthesis Y Choi, Y Chi, J Lau, J Cong IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022 | 3 | 2022 |
| TAPA: A scalable task-parallel dataflow programming framework for modern FPGAs with co-optimization of HLS and physical design L Guo*, Y Chi*, J Lau*, L Song, X Tian, M Khatti, W Qiao, J Wang, E Ustun, ... arXiv preprint arXiv:2209.02663, 2022 | | 2022 |
| Student cluster competition 2017, team Tsinghua University: Reproducing vectorization of the tersoff multi-body potential on the Intel Skylake and NVIDIA Volta architectures J Lau, Y Li, L Xie, Q Xie, B Li, Y Chen, G Feng, J Yu, X Yu, M Wang, ... Parallel Computing 78, 47-53, 2018 | | 2018 |
Jingsheng Jason CongVolgenau Chair for Engineering Excellence, Computer Science and Electrical Engineering, UniversityVerified email at cs.ucla.edu
