Stochastic computing improves the timing-error tolerance and latency of turbo decoders: Design guidelines and tradeoffs I Perez-Andrade, S Zhong, RG Maunder, BM Al-Hashimi, L Hanzo IEEE Access 4, 1008-1038, 2016 | 19 | 2016 |
Analysis of voltage-and clock-scaling-induced timing errors in stochastic LDPC decoders I Perez-Andrade, X Zuo, RG Maunder, BM Al-Hashimi, L Hanzo 2013 IEEE Wireless Communications and Networking Conference (WCNC), 4293-4298, 2013 | 17 | 2013 |
Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: A tutorial and a design example X Zuo, I Perez-Andrade, RG Maunder, BM Al-Hashimi, L Hanzo IEEE Access 4, 1607-1629, 2016 | 11 | 2016 |
Low latency polar coding and decoding by merging of states of the polar code graph R Maunder, M Brejza, S Zhong, I Perez-Andrade, T Chen US Patent 11,165,448, 2021 | 5 | 2021 |
Polar coder with logical three-dimensional memory, communicaton unit, integrated circuit and method therefor R Maunder, M Brejza, S Zhong, I Andrade, T Chen US Patent 11,146,294, 2021 | 4 | 2021 |
Fully parallel turbo decoding R Maunder, A Li, I Perez-Andrade US Patent 10,439,645, 2019 | 4 | 2019 |
Blockwise parallel frozen bit generation for polar codes R Maunder, M Brejza, S Zhong, I Perez-Andrade, T Chen US Patent 11,043,972, 2021 | 3 | 2021 |
Polar encoder, communication unit, integrated circuit and method therefor R Maunder, M Brejza, S Zhong, I Andrade, T Chen US Patent 11,290,129, 2022 | 1 | 2022 |
Timing-error-tolerant iterative decoders I Perez Andrade University of Southampton, 2016 | 1 | 2016 |
Electronic device with bit pattern generation, integrated circuit and method for polar coding R Maunder, M Brejza, S Zhong, I Perez-Andrade, T Chen US Patent 11,265,020, 2022 | | 2022 |
Polar decoder with LLR-domain computation of f-function and g-function R Maunder, M Brejza, S Zhong, I Perez-Andrade, T Chen US Patent 11,190,221, 2021 | | 2021 |
Fully parallel turbo decoding R MAUNDER, A Li, I PEREZ-ANDRADE | | 2017 |
Supplemental data of Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Trade-offs I Perez Andrade, S Zhong, R Maunder, B Al-Hashimi, L Hanzo University of Southampton, 2015 | | 2015 |