Syed Muhammad Yasser Sherazi
Syed Muhammad Yasser Sherazi
R&D Team Leader, IMEC
Verified email at imec.be
Title
Cited by
Cited by
Year
Benchmarking of Standard-Cell Based Memories in the Sub-Domain in 65-nm CMOS Technology
P Meinerzhagen, SMY Sherazi, A Burg, JN Rodrigues
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (2 …, 2011
802011
A receiver architecture for devices in wireless body area networks
H Sjoland, JB Anderson, C Bryant, R Chandra, O Edfors, AJ Johansson, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (1 …, 2012
442012
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
392018
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ...
2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016
382016
Standard cell design in N7: EUV vs. immersion
B Chava, D Rio, Y Sherazi, D Trivkovic, W Gillijns, P Debacker, ...
Design-Process-Technology Co-optimization for Manufacturability IX, 9 (Proc …, 2015
372015
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS
P Meinerzhagen, O Andersson, B Mohammadi, Y Sherazi, A Burg, ...
2012 Proceedings of the ESSCIRC (ESSCIRC), 321-324, 2012
362012
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
352017
DTCO at N7 and beyond: patterning and electrical compromises and opportunities
J Ryckaert, P Raghavan, P Schuddinck, HB Trong, A Mallik, SS Sakhare, ...
Design-Process-Technology Co-optimization for Manufacturability IX 9427 (doi …, 2015
352015
Impact of a SADP flow on the design and process for N10/N7 metal layers
W Gillijns, SMY Sherazi, D Trivkovic, B Chava, B Vandewalle, V Gerousis, ...
Design-Process-Technology Co-optimization for Manufacturability IX 9427 (doi …, 2015
252015
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
232017
Low track height standard cell design in iN7 using scaling boosters
SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ...
Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017
222017
Architectural strategies in standard-cell design for the 7 nm and beyond technology node
SMY Sherazi, B Chava, P Debacker, MG Bardon, P Schuddinck, F Firouzi, ...
Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (1), 013507, 2016
202016
Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform
VMB Carballo, J Bekaert, M Mao, BK Kotowska, S Larivière, I Ciofi, ...
Extreme Ultraviolet (EUV) Lithography VIII 10143, 1014318, 2017
192017
The Complementary FET (CFET) for CMOS scaling beyond N3
J Ryckaert, P Schuddinck, P Weckx, G Bouche, B Vincent, J Smith, ...
2018 IEEE Symposium on VLSI Technology, 141-142, 2018
182018
Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells
MG Bardon, Y Sherazi, D Jang, D Yakimets, P Schuddinck, R Baert, ...
2018 IEEE Symposium on VLSI Technology, 143-144, 2018
122018
Design and pitch scaling for affordable node transition and EUV insertion scenario
R Kim, J Ryckaert, P Raghavan, Y Sherazi, P Debacker, D Trivkovic, ...
Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017
122017
Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet
SMY Sherazi, M Cupak, P Weckx, O Zografos, D Jang, P Debacker, ...
Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019
102019
Synthesis strategies for sub-VT systems
P Meinerzhagen, O Andersson, Y Sherazi, A Burg, J Rodrigues
Circuit Theory and Design (ECCTD), 2011 20th European Conference on, 552-555, 2011
102011
Sizing of dual-VT gates for sub-VT circuits
B Mohammadi, SMY Sherazi, JN Rodrigues
2012 IEEE Subthreshold Microelectronics Conference (SubVT), 1-3, 2012
82012
DTCO exploration for efficient standard cell power rails
B Chava, J Ryckaert, L Mattii, SMY Sherazi, P Debacker, A Spessot, ...
Design-Process-Technology Co-optimization for Manufacturability XII 10588 …, 2018
72018
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