| Hardware/software co-exploration of neural architectures W Jiang, L Yang, EHM Sha, Q Zhuge, S Gu, S Dasgupta, Y Shi, J Hu (Best Paper Award) IEEE Transactions on Computer-Aided Design of Integrated …, 2020 | 179 | 2020 |
| Accuracy vs. efficiency: Achieving both through fpga-implementation aware neural architecture search W Jiang, X Zhang, EHM Sha, L Yang, Q Zhuge, Y Shi, J Hu (Best Paper Nomination) Proceedings of the 56th Annual Design Automation …, 2019 | 174 | 2019 |
| Co-exploration of neural architectures and heterogeneous asic accelerator designs targeting multiple tasks L Yang, Z Yan, M Li, H Kwon, L Lai, T Krishna, V Chandra, W Jiang, Y Shi 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 139 | 2020 |
| Accelerating transformer-based deep learning models on fpgas using column balanced block pruning H Peng, S Huang, T Geng, A Li, W Jiang, H Liu, S Wang, C Ding 2021 22nd International Symposium on Quality Electronic Design (ISQED), 142-148, 2021 | 103 | 2021 |
| Achieving super-linear speedup across multi-fpga for real-time dnn inference W Jiang, EHM Sha, X Zhang, L Yang, Q Zhuge, Y Shi, J Hu (Best Paper Nomination @ CODES+ISSS'19) ACM Transactions on Embedded …, 2019 | 95 | 2019 |
| Device-circuit-architecture co-exploration for computing-in-memory neural accelerators W Jiang, Q Lou, Z Yan, L Yang, J Hu, XS Hu, Y Shi IEEE Transactions on Computers 70 (4), 595-605, 2020 | 94 | 2020 |
| On neural architecture search for resource-constrained hardware platforms Q Lu, W Jiang, X Xu, Y Shi, J Hu arXiv preprint arXiv:1911.00105, 2019 | 93 | 2019 |
| A Co-Design Framework of Neural Networks and Quantum Circuits Towards Quantum Advantage W Jiang, J Xiong, Y Shi Nature Communications 12 (1), 1-13, 2021 | 91 | 2021 |
| Standing on the shoulders of giants: Hardware and neural architecture co-search with hot start W Jiang, L Yang, S Dasgupta, J Hu, Y Shi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 84 | 2020 |
| A new design of in-memory file system based on file virtual address framework EHM Sha, X Chen, Q Zhuge, L Shi, W Jiang (Editor’s pick of the year 2016) IEEE Transactions on Computers 65 (10 …, 2016 | 67 | 2016 |
| Ms-nas: Multi-scale neural architecture search for medical image segmentation X Yan, W Jiang, Y Shi, C Zhuo Medical Image Computing and Computer Assisted Intervention–MICCAI 2020: 23rd …, 2020 | 66 | 2020 |
| Variational quantum pulse learning Z Liang, H Wang, J Cheng, Y Ding, H Ren, Z Gao, Z Hu, DS Boning, ... 2022 IEEE International Conference on Quantum Computing and Engineering (QCE …, 2022 | 56 | 2022 |
| A length adaptive algorithm-hardware co-design of transformer on fpga through sparse attention and dynamic pipelining H Peng, S Huang, S Chen, B Li, T Geng, A Li, W Jiang, W Wen, J Bi, H Liu, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 1135-1140, 2022 | 53 | 2022 |
| Co-exploring neural architecture and network-on-chip design for real-time artificial intelligence L Yang, W Jiang, W Liu, HM Edwin, Y Shi, J Hu (Best Paper Nomination) 2020 25th Asia and South Pacific Design Automation …, 2020 | 47 | 2020 |
| Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip W Liu, L Yang, W Jiang, L Feng, N Guan, W Zhang, N Dutt IEEE Transactions on Computers 67 (12), 1818-1834, 2018 | 45 | 2018 |
| When neural architecture search meets hardware implementation: from hardware awareness to co-design X Zhang, W Jiang, Y Shi, J Hu 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 25-30, 2019 | 43 | 2019 |
| Heterogeneous fpga-based cost-optimal design for timing-constrained cnns W Jiang, EHM Sha, Q Zhuge, L Yang, X Chen, J Hu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 41 | 2018 |
| Quest: Graph transformer for quantum circuit reliability estimation H Wang, P Liu, J Cheng, Z Liang, J Gu, Z Li, Y Ding, W Jiang, Y Shi, ... arXiv preprint arXiv:2210.16724, 2022 | 39 | 2022 |
| Application mapping and scheduling for network-on-chip-based multiprocessor system-on-chip with fine-grain communication optimization L Yang, W Liu, W Jiang, M Li, J Yi, EHM Sha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016 | 39 | 2016 |
| FoToNoC: A folded torus-like network-on-chip based many-core systems-on-chip in the dark silicon era L Yang, W Liu, W Jiang, M Li, P Chen, EHM Sha IEEE Transactions on Parallel and Distributed Systems 28 (7), 1905-1918, 2016 | 38 | 2016 |
Lei YangGeorge Mason UniversityVerified email at gmu.edu
