Ryusuke Egawa
Ryusuke Egawa
東北大学 准教授
確認したメール アドレス: tohoku.ac.jp
タイトル
引用先
引用先
Xevolver: An XML-based code translation framework for supporting HPC application migration
H Takizawa, S Hirasawa, Y Hayashi, R Egawa, H Kobayashi
2014 21st International Conference on High Performance Computing (HiPC), 1-11, 2014
432014
Performance evaluation of NEC SX-9 using real science and engineering applications
T Soga, A Musa, Y Shimomura, R Egawa, K Itakura, H Takizawa, K Okabe, ...
Proceedings of the Conference on High Performance Computing Networking …, 2009
422009
A history-based job scheduling mechanism for the vector computing cloud
Y Murata, R Egawa, M Higashida, H Kobayashi
2010 10th IEEE/IPSJ International Symposium on Applications and the Internet …, 2010
322010
Scaling up of wave pipelines
M Fukase, T Sato, R Egawa, T Nakamura
VLSI Design 2001. Fourteenth International Conference on VLSI Design, 439-445, 2001
322001
Power-aware dynamic cache partitioning for CMPs
I Kotera, K Abe, R Egawa, H Takizawa, H Kobayashi
Transactions on high-performance embedded architectures and compilers III …, 2011
262011
Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE
R Egawa, K Komatsu, S Momose, Y Isobe, A Musa, H Takizawa, ...
The Journal of Supercomputing 73 (9), 3948-3976, 2017
252017
Modeling of cache access behavior based on Zipf's law
I Kotera, R Egawa, H Takizawa, H Kobayashi
Proceedings of the 9th workshop on MEmory performance: DEaling with …, 2008
222008
Designing a wave-pipelined vector processor
M Fukase
SASIMI 2001, Oct., 2001
222001
Evaluation of fine grain 3-D integrated arithmetic units
R Egawa, J Taday, H Kobayashi, G Gotoy
2009 IEEE International Conference on 3D System Integration, 1-8, 2009
212009
Break-through of Suparscalar Processors by Multifunctional Wave-Pipelines
M FUKASE
Proc. of 9th NASA Symposium on VLSI Design, Nov. 2000, 2000
212000
Parallel processing of the Building-Cube Method on a GPU platform
K Komatsu, T Soga, R Egawa, H Takizawa, H Kobayashi, S Takahashi, ...
Computers & Fluids 45 (1), 122-128, 2011
182011
Effects of MSHR and prefetch mechanisms on an on-chip cache of the vector architecture
A Musa, Y Sato, T Soga, R Egawa, H Takizawa, K Okabe, H Kobayashi
2008 IEEE International Symposium on Parallel and Distributed Processing …, 2008
162008
A wave-pipelined biprocessor achieving remarkable compatibility between low power and high speed
M Fukase
Proc. of 10^< th> NASA Symposium on VLSI Design, Albuquerque, Mar. 2002, 2002
142002
A utility-based double auction mechanism for efficient grid resource allocation
C Satayapiwat, R Egawa, H Takizawa, H Kobayashi
2008 IEEE International Symposium on Parallel and Distributed Processing …, 2008
132008
A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers
J Tada, R Egawa, K Kawai, H Kobayashi, G Goto
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE …, 2011
122011
A cache-aware thread scheduling policy for multi-core processors
M Sato, I Kotera, R Egawa, H Takizawa, H Kobayashi
Proceedings of the IASTED International Conference on Parallel and …, 2009
122009
First experiences with NEC SX-9
H Kobayashi, R Egawa, H Takizawa, K Okabe, A Musa, T Soga, ...
High Performance Computing on Vector Systems 2008, 3-11, 2009
112009
A shared cache for a chip multi vector processor
A Musa, Y Sato, T Soga, K Okabe, R Egawa, H Takizawa, H Kobayashi
Proceedings of the 9th workshop on MEmory performance: DEaling with …, 2008
112008
An on-chip cache design for vector processors
A Musa, Y Sato, R Egawa, H Takizawa, K Okabe, H Kobayashi
Proceedings of the 2007 workshop on MEmory performance: DEaling with …, 2007
112007
A systolic memory architecture for fast codebook design based on mmpdcl algorithm
K Sano, C Takagi, R Egawa, K Suzuki, T Nakamura
International Conference on Information Technology: Coding and Computing …, 2004
112004
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論文 1–20