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Kota Shiba
Kota Shiba
Other namesŽÄ N‘¾
Senior Engineer, TSMC
Verified email at tsmc.com - Homepage
Title
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Year
A 96-MB 3D-stacked SRAM using inductive coupling with 0.4-V transmitter, termination scheme and 12: 1 SerDes in 40-nm CMOS
K Shiba, T Omori, K Ueyoshi, S Takamaeda-Yamazaki, M Motomura, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 692-703, 2020
222020
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous c
K Shiba, M Okada, A Kosuge, M Hamada, T Kuroda
IEEE Journal of Solid-State Circuits 58 (7), 2075-2086, 2022
112022
A 183.4 nJ/inference 152.8 ƒÊW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
A Kosuge, R Sumikawa, YC Hsu, K Shiba, M Hamada, T Kuroda
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and c, 2023
82023
A 13.7 ƒÊJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
YC Hsu, A Kosuge, R Sumikawa, K Shiba, M Hamada, T Kuroda
2022 IEEE Hot Chips 34 Symposium (HCS), 1-14, 2022
62022
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
K Shiba, M Okada, A Kosuge, M Hamada, T Kuroda
2022 IEEE Hot Chips 34 Symposium (HCS), 1-14, 2022
52022
A 3D-stacked SRAM using inductive coupling with low-voltage transmitter and 12: 1 SerDes
K Shiba, T Omori, K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, ...
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
52020
3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via
K Shiba, M Hamada, T Kuroda
Japanese Journal of Applied Physics 59 (SG), SGGL04, 2020
52020
A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS
K Shiba, T Omori, M Hamada, T Kuroda
Proceedings of the 26th Asia and South Pacific Design Automation Conference c, 2021
42021
A Fully Synthesized 13.7 ƒÊJ/prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network
YC Hsu, A Kosuge, R Sumikawa, K Shiba, M Hamada, T Kuroda
Proceedings of the 28th Asia and South Pacific Design Automation Conference c, 2023
32023
A 1.2nJ/Classification 2.4mm2 Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18undefinedm CMOS
R Sumikawa, K Shiba, A Kosuge, M Hamada, T Kuroda
Extended Abstracts of the 2022 International Conference on Solid State c, 2022
32022
A 12.8-Gb/s 0.5-pJ/b Encoding-Less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET
K Shiba, M Okada, A Kosuge, M Hamada, T Kuroda
IEEE Solid-State Circuits Letters 6, 65-68, 2023
22023
1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 ƒÊm CMOS
R Sumikawa, K Shiba, A Kosuge, M Hamada, T Kuroda
Japanese Journal of Applied Physics 62 (SC), SC1019, 2023
22023
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0. 37 Compression Format
K Shiba, M Okada, A Kosuge, M Hamada, T Kuroda
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS), 99-103, 2022
22022
A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna
S Shibata, R Miura, Y Sawabe, K Shiba, A Kosuge, M Hamada, T Kuroda
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021
22021
Crosstalk analysis and countermeasures of high-density multi-hop inductive coupling interface for 3D-stacked memory
K Shiba, T Omori, M Okada, M Hamada, T Kuroda
2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 1-3, 2020
22020
3D SoC design with TSV-less power supply employing highly doped silicon via
K Shiba, M Hamada, T Kuroda
Proc. JSAP Int. Conf. Solid State Devices Mater., 515-516, 2019
22019
A183. 4-nJ/Inference 152.8-ƒÊW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique
R Sumikawa, A Kosuge, YC Hsu, K Shiba, M Hamada, T Kuroda
IEEE Solid-State Circuits Letters, 2023
12023
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface
K SHIBA, A KOSUGE, M HAMADA, T KURODA
IEICE Transactions on Electronics 106 (7), 391-394, 2023
12023
A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-ƒÊm CMOS
S Shibata, R Miura, Y Sawabe, K Shiba, A Kosuge, M Hamada, T Kuroda
IEEE Solid-State Circuits Letters 5, 268-271, 2022
12022
A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
K Shiba, M Okada, A Kosuge, M Hamada, T Kuroda
2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022
12022
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