| Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs KT Sundararajan, V Porpodas, TM Jones, NP Topham, B Franke IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 82 | 2012 |
| Smart cache: A self adaptive cache architecture for energy efficiency KT Sundararajan, TM Jones, N Topham 2011 International Conference on Embedded Computer Systems: Architectures …, 2011 | 56 | 2011 |
| The smart cache: An energy-efficient cache architecture through dynamic adaptation KT Sundararajan, TM Jones, NP Topham International Journal of Parallel Programming 41 (2), 305-330, 2013 | 20 | 2013 |
| RECAP: region-aware cache partitioning KT Sundararajan, TM Jones, NP Topham 2013 IEEE 31st international conference on computer design (ICCD), 294-301, 2013 | 18 | 2013 |
| A reconfigurable cache architecture for energy efficiency KT Sundararajan, TM Jones, N Topham Proceedings of the 8th ACM International Conference on Computing Frontiers, 1-2, 2011 | 10 | 2011 |
| Energy-efficient cache partitioning for future cmps KT Sundararajan, TM Jones, NP Topham Proceedings of the 21st international conference on Parallel architectures …, 2012 | 7 | 2012 |
| Energy Efficient Cache Architectures for Single, Multi and Many Core Processors KT Sundararajan https://www.era.lib.ed.ac.uk/handle/1842/9916, 2013 | 5* | 2013 |
| Efficient Memory Organization C Basto, KT Sundararajan US Patent App. 14/505,421, 2015 | 4 | 2015 |
| Buffer circuitry for store to load forwarding KT Sundararajan US Patent 12,147,707, 2024 | | 2024 |
| Predicting aliasing bits in a virtually indexed physically tagged cache KT Sundararajan US Patent 12,124,375, 2024 | | 2024 |
| Management circuitry for a least recently used memory management process KT Sundararajan US Patent 12,124,379, 2024 | | 2024 |
| Conversion of a clean unique request to a read unique request by a memory coherency manager circuit KT Sundararajan US Patent 12,045,167, 2024 | | 2024 |
| Varied validity bit placement in tag bits of a memory KT Sundararajan US Patent 12,026,094, 2024 | | 2024 |
| Memory coherence protocol for communicating data associated with a shared state between processor cores KT Sundararajan US Patent App. 17/974,881, 2024 | | 2024 |
| Conflict detection and address arbitration for routing scatter and gather transactions for a memory bank KT Sundararajan US Patent App. 17/962,683, 2024 | | 2024 |
| Store instruction merging with pattern detection KT Sundararajan US Patent App. 17/956,034, 2024 | | 2024 |
| Atomic correction of single bit errors within a memory KT Sundararajan US Patent 11,928,024, 2024 | | 2024 |
| Energy efficient tag partitioning in cache memory KT Sundararajan US Patent 11,899,586, 2024 | | 2024 |
Timothy M. JonesUniversity of Cambridge確認したメール アドレス: cl.cam.ac.uk
