BRein memory: A single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, ... IEEE Journal of Solid-State Circuits 53 (4), 983-994, 2017 | 167 | 2017 |

QUEST: A 7.49 TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, J Kadomoto, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 216-218, 2018 | 100 | 2018 |

BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS K Ando, K Ueyoshi, K Orimo, H Yonekawa, S Sato, H Nakahara, M Ikebe, ... 2017 Symposium on VLSI Circuits, C24-C25, 2017 | 93 | 2017 |

STATICA: A 512-Spin 0.25 M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions K Yamamoto, K Kawamura, K Ando, N Mertig, T Takemoto, M Yamaoka, ... IEEE Journal of Solid-State Circuits 56 (1), 165-178, 2020 | 62 | 2020 |

QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, M Hamada, ... IEEE Journal of Solid-State Circuits 54 (1), 186-196, 2018 | 58 | 2018 |

7.3 STATICA: A 512-Spin 0.25 M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete … K Yamamoto, K Ando, N Mertig, T Takemoto, M Yamaoka, H Teramoto, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 138-140, 2020 | 27 | 2020 |

STATICA: A 512-spin 0.25 M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin … K Yamamoto, K Ando, N Mertig, T Takemoto, M Yamaoka, H Teramoto, ... IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, 138-140, 2020 | 26 | 2020 |

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0 TOPS/W for CIFAR-100 and ImageNet K Hirose, J Yu, K Ando, Y Okoshi, ÁL García-Arias, J Suzuki, T Van Chu, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 18 | 2022 |

Dither NN: An accurate neural network with dithering for low bit-precision hardware K Ando, K Ueyoshi, Y Oba, K Hirose, R Uematsu, T Kudo, M Ikebe, T Asai, ... 2018 International Conference on Field-Programmable Technology (FPT), 6-13, 2018 | 11 | 2018 |

In-memory area-efficient signal streaming processor design for binary neural networks H Yonekawa, S Sato, H Nakahara, K Ando, K Ueyoshi, K Hirose, K Orimo, ... 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 9 | 2017 |

Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension K Kawamura, J Yu, D Okonogi, S Jimbo, G Inoue, A Hyodo, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 42-44, 2023 | 8 | 2023 |

Quantization error-based regularization for hardware-aware neural network training K Hirose, R Uematsu, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura, ... Nonlinear Theory and Its Applications, IEICE 9 (4), 453-465, 2018 | 7 | 2018 |

Fpga architecture for feed-forward sequential memory network targeting long-term time-series forecasting K Orimo, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura 2016 International Conference on ReConFigurable Computing and FPGAs …, 2016 | 7 | 2016 |

Quantization error-based regularization in neural networks K Hirose, K Ando, K Ueyoshi, M Ikebe, T Asai, M Motomura, ... International Conference on Innovative Techniques and Applications of …, 2017 | 6 | 2017 |

Multicoated Supermasks Enhance Hidden Networks Y Okoshi, ÁL Garcı́a-Arias, K Hirose, K Ando, K Kawamura, T Van Chu, ... International Conference on Machine Learning, 17045-17055, 2022 | 5 | 2022 |

Exploring optimized accelerator design for binarized convolutional neural networks K Ueyoshi, K Ando, K Orimo, M Ikebe, T Asai, M Motomura 2017 International Joint Conference on Neural Networks (IJCNN), 2510-2516, 2017 | 4 | 2017 |

A 3D-stacked SRAM using inductive coupling with low-voltage transmitter and 12: 1 SerDes K Shiba, T Omori, K Ueyoshi, K Ando, K Hirose, S Takamaeda-Yamazaki, ... 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 3 | 2020 |

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks K Ando, K Ueyoshi, Y Oba, K Hirose, R Uematsu, T Kudo, M Ikebe, T Asai, ... IEICE Transactions on Information and Systems 102 (12), 2341-2353, 2019 | 3 | 2019 |

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators T Kudo, K Ueyoshi, K Ando, K Hirose, R Uematsu, Y Oba, M Ikebe, T Asai, ... 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core …, 2018 | 3 | 2018 |

Accelerating deep learning by binarized hardware S Takamaeda-Yamazaki, K Ueyoshi, K Ando, R Uematsu, K Hirose, ... 2017 Asia-Pacific Signal and Information Processing Association Annual …, 2017 | 3 | 2017 |