Pablo Ibáñez Marín
Pablo Ibáñez Marín
Universidad Zaragoza, I3A, Departamento de Informática e Ingeniería de Sistemas
確認したメール アドレス: unizar.es - ホームページ
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引用先
The reuse cache: Downsizing the shared last-level cache
J Albericio, P Ibáñez, V Viñals, JM Llabería
2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013
582013
Store buffer design in first-level multibanked data caches
EF Torres, P Ibánez, V Viñals, JM Llabería
32nd International Symposium on Computer Architecture (ISCA'05), 469-480, 2005
502005
Multi-level adaptive prefetching based on performance gradient tracking
LM Ramos, JL Briz, PE Ibáñez, V Viñals
Journal of Instruction-Level Parallelism 13, 1-14, 2011
252011
Exploiting reuse locality on inclusive shared last-level caches
J Albericio, P Ibánez, V Viñals, JM Llabería
ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-19, 2013
232013
Concertina: Squeezing in cache content to operate at near-threshold voltage
A Ferreron, D Suarez-Gracia, J Alastruey-Benede, T Monreal-Arnal, ...
IEEE Transactions on Computers 65 (3), 755-769, 2015
182015
A review of High Performance Computing foundations for scientists
P García-Risueño, PE Ibáñez
International journal of modern physics C 23 (07), 1230001, 2012
142012
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache
J Albericio, R Gran, P Ibánez, V Viñals, JM Llabería
ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-20, 2012
132012
Characterization of Apache web server with Specweb2005
A Bosque, P Ibañez, V Viñals, P Stenström, JM Llabería
Proceedings of the 2007 workshop on Memory performance: Dealing with …, 2007
132007
Data prefetching in a cache hierarchy with high bandwidth and capacity
LM Ramos, JL Briz, PE Ibáñez, V Viñals
ACM SIGARCH Computer Architecture News 35 (4), 37-44, 2007
132007
Characterization and improvement of load/store cache-based prefetching
P Ibáñez, V Viñals, JL Briz, MJ Garzarán
Proceedings of the 12th international conference on Supercomputing, 369-376, 1998
131998
A methodology to characterize critical section bottlenecks in dsm multiprocessors
B Sahelices, P Ibánez, V Viñals, JM Llabería
European Conference on Parallel Processing, 149-161, 2009
92009
Hardware prefetching in bus-based multiprocessors: pattern characterization and cost-effective hardware
MJ Garzaran, JL Brit, PE Ibáñez, V Vinals
Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing …, 2001
82001
Warm Time-sampling: Fast and Accurate Cycle-level Simulation of Cache Memory
LM Jimeno, O Pablo
In Proc. of the 22nd Euromicro Conf. Short Contrib. pp: 3944, 1996
7*1996
Modeling load address behaviour through recurrences
L Ramos, P Ibáñez, V Vinals, JM Llabería
2000 IEEE International Symposium on Performance Analysis of Systems and …, 2000
62000
Low-cost adaptive data prefetching
LM Ramos, JL Briz, PE Ibáñez, V Viñals
European Conference on Parallel Processing, 327-336, 2008
52008
Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP
A Navarro-Torres, J Alastruey-Benedé, P Ibáñez-Marín, V Viñals-Yúfera
Plos one 14 (8), e0220135, 2019
42019
Accelerating sequence alignments based on fm-index using the intel knl processor
JM Herruzo, S González-Navarro, P Ibanez-Marin, V Vinals-Yufera, ...
IEEE/ACM transactions on computational biology and bioinformatics 17 (4 …, 2018
42018
Speeding-up synchronizations in dsm multiprocessors
A De Dios, B Sahelices, P Ibáñez, V Viñals, JM Llabería
European Conference on Parallel Processing, 473-484, 2006
42006
Software demand, hardware supply
J Alastruey, JL Briz, P Ibáñez, V Viñals
IEEE Micro 26 (4), 72-82, 2006
42006
Contents management in first-level multibanked data caches
EF Torres, P Ibañez, V Viñals, JM Llabería
European Conference on Parallel Processing, 516-524, 2004
42004
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