| Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier K Hasegawa, M Yanagisawa, N Togawa 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 213 | 2017 |
| Hardware Trojans classification for gate-level netlists based on machine learning K Hasegawa, M Oya, M Yanagisawa, N Togawa 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System …, 2016 | 175 | 2016 |
| Hardware Trojans classification for gate-level netlists using multi-layer neural networks K Hasegawa, M Yanagisawa, N Togawa 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System …, 2017 | 147 | 2017 |
| A score-based classification method for identifying hardware-trojans at gate-level netlists M Oya, Y Shi, M Yanagisawa, N Togawa 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 465-470, 2015 | 143 | 2015 |
| Scan-based side-channel attack against RSA cryptosystems using scan signatures R Nara, K Satoh, M Yanagisawa, T Ohtsuki, N Togawa IEICE transactions on fundamentals of electronics, communications and …, 2010 | 99 | 2010 |
| Scan-based attack against elliptic curve cryptosystems R Nara, N Togawa, M Yanagisawa, T Ohtsuki 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 407-412, 2010 | 99 | 2010 |
| A scan-based attack based on discriminators for AES cryptosystems R Nara, N Togawa, M Yanagisawa, T Ohtsuki IEICE transactions on fundamentals of electronics, communications and …, 2009 | 63 | 2009 |
| A hardware-Trojan classification method using machine learning at gate-level netlists based on Trojan features K Hasegawa, M Yanagisawa, N Togawa IEICE Transactions on Fundamentals of Electronics, Communications and …, 2017 | 61 | 2017 |
| Dynamically changeable secure scan architecture against scan-based side channel attack Y Atobe, Y Shi, M Yanagisawa, N Togawa 2012 International SoC Design Conference (ISOCC), 155-158, 2012 | 58 | 2012 |
| Partially-parallel LDPC decoder based on high-efficiency message-passing algorithm K Shimizu, T Ishikawa, N Togawa, T Ikenaga, S Goto 2005 International Conference on Computer Design, 503-510, 2005 | 55 | 2005 |
| Performance comparison of typical binary-integer encodings in an Ising machine K Tamura, T Shirai, H Katsura, S Tanaka, N Togawa IEEE Access 9, 81032-81039, 2021 | 54 | 2021 |
| Designing hardware trojans and their detection based on a SVM-based approach T Inoue, K Hasegawa, M Yanagisawa, N Togawa 2017 IEEE 12th international conference on ASIC (ASICON), 811-814, 2017 | 51 | 2017 |
| Hardware trojan detection utilizing machine learning approaches K Hasegawa, Y Shi, N Togawa 2018 17th IEEE International Conference On Trust, Security And Privacy In …, 2018 | 45 | 2018 |
| Exact and fast L1 cache simulation for embedded systems N Tojo, N Togawa, M Yanagisawa, T Ohtsuki 2009 Asia and South Pacific Design Automation Conference, 817-822, 2009 | 45 | 2009 |
| Secure scan design with dynamically configurable connection Y Atobe, Y Shi, M Yanagisawa, N Togawa 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing …, 2013 | 39 | 2013 |
| Maple: A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays N Togawa, M Sato, T Ohtsuki IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 1994 | 38 | 1994 |
| Scan-based attack against DES cryptosystems using scan signatures H Kodera, M Yanagisawa, N Togawa 2012 IEEE Asia Pacific Conference on Circuits and Systems, 599-602, 2012 | 37 | 2012 |
| An Ising model mapping to solve rectangle packing problem K Terada, D Oku, S Kanamaru, S Tanaka, M Hayashi, M Yamaoka, ... 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2018 | 35 | 2018 |
| A hardware-Trojan classification method utilizing boundary net structures K Hasegawa, M Yanagisawa, N Togawa 2018 IEEE international conference on consumer electronics (ICCE), 1-4, 2018 | 33 | 2018 |
| Robust secure scan design against scan-based differential cryptanalysis Y Shi, N Togawa, M Yanagisawa, T Ohtsuki IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (1), 176-181, 2011 | 32 | 2011 |
