| FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS hybrid templates Y Guan, H Liang, N Xu, W Wang, S Shi, X Chen, G Sun, W Zhang, J Cong 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 406 | 2017 |
| Semantics-based online malware detection: Towards efficient real-time protection against malware S Das, Y Liu, W Zhang, M Chandramohan IEEE transactions on information forensics and security 11 (2), 289-302, 2015 | 228 | 2015 |
| A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip H Gu, J Xu, W Zhang 2009 Design, Automation & Test in Europe Conference & Exhibition, 3-8, 2009 | 209 | 2009 |
| A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip WZ Huaxi Gu, Kwai Hung Mo, Jiang Xu IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009 | 202* | 2009 |
| Crosstalk noise and bit error rate analysis for optical network-on-chip Y Xie, M Nikdast, J Xu, W Zhang, Q Li, X Wu, Y Ye, X Wang, W Liu Proceedings of the 47th Design Automation Conference, 657-660, 2010 | 157 | 2010 |
| A NoC traffic suite based on real applications W Liu, J Xu, X Wu, Y Ye, X Wang, W Zhang, M Nikdast, Z Wang 2011 IEEE computer society annual symposium on VLSI, 66-71, 2011 | 151 | 2011 |
| COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 430-437, 2017 | 148 | 2017 |
| 3-D mesh-based optical network-on-chip for multiprocessor system-on-chip Y Ye, J Xu, B Huang, X Wu, W Zhang, X Wang, M Nikdast, Z Wang, W Liu, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 128 | 2013 |
| A performance analysis framework for optimizing OpenCL applications on FPGAs Z Wang, B He, W Zhang, S Jiang 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 117 | 2016 |
| Design exploration of hybrid CMOS and memristor circuit by new modified nodal analysis W Fei, H Yu, W Zhang, KS Yeo IEEE Transactions on very large scale integration (VLSI) systems 20 (6 …, 2011 | 103 | 2011 |
| A hierarchical hybrid optical-electronic network-on-chip KH Mo, Y Ye, X Wu, W Zhang, W Liu, J Xu 2010 IEEE Computer Society Annual Symposium on VLSI, 327-332, 2010 | 97 | 2010 |
| Formal worst-case analysis of crosstalk noise in mesh-based optical networks-on-chip Y Xie, M Nikdast, J Xu, X Wu, W Zhang, Y Ye, X Wang, Z Wang, W Liu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (10 …, 2012 | 95 | 2012 |
| Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine B Liu, M Hu, H Li, ZH Mao, Y Chen, T Huang, W Zhang Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 89 | 2013 |
| A torus-based hierarchical optical-electronic network-on-chip for multiprocessor system-on-chip Y Ye, J Xu, X Wu, W Zhang, W Liu, M Nikdast ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (1), 1-26, 2012 | 85 | 2012 |
| A fine-grained control flow integrity approach against runtime memory attacks for embedded systems S Das, W Zhang, Y Liu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (11 …, 2016 | 80 | 2016 |
| A new RNS based DA approach for inner product computation CH Vun, AB Premkumar, W Zhang IEEE Transactions on Circuits and Systems I: Regular Papers 60 (8), 2139-2152, 2013 | 80 | 2013 |
| Systematic analysis of crosstalk noise in folded-torus-based optical networks-on-chip M Nikdast, J Xu, X Wu, W Zhang, Y Ye, X Wang, Z Wang, Z Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 75 | 2014 |
| Melia: A mapreduce framework on opencl-based fpgas Z Wang, S Zhang, B He, W Zhang IEEE Transactions on Parallel and Distributed Systems 27 (12), 3547-3560, 2016 | 72 | 2016 |
| System-level modeling and analysis of thermal effects in optical networks-on-chip Y Ye, J Xu, X Wu, W Zhang, X Wang, M Nikdast, Z Wang, W Liu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 292-305, 2012 | 69 | 2012 |
| Performance modeling and directives optimization for high-level synthesis on FPGA J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 64 | 2019 |
Jiang XuHong Kong University of Science and TechnologyVerified email at ust.hk
