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Erik H. D'Hollander
Erik H. D'Hollander
Professor of Computer Science, Ghent University
Verified email at elis.ugent.be
Title
Cited by
Cited by
Year
Reuse distance as a metric for cache behavior
K Beyls, E D’Hollander
Proceedings of the IASTED Conference on Parallel and Distributed Computing …, 2001
2572001
Generating cache hints for improved program efficiency
K Beyls, EH D’Hollander
Journal of Systems Architecture 51 (4), 223-250, 2005
1192005
Partitioning and labeling of loops by unimodular transformations
EH D'Hollander
IEEE Transactions on Parallel & Distributed Systems 3 (04), 465-476, 1992
961992
Using hammock graphs to structure programs
F Zhang, EH D'Hollander
IEEE Transactions on Software Engineering 30 (4), 231-245, 2004
822004
Discovery of locality-improving refactorings by reuse path analysis
K Beyls, EH D’Hollander
International Conference on High Performance Computing and Communications …, 2006
772006
Reuse distance-based cache hint selection
K Beyls, EH D’Hollander
European Conference on Parallel Processing, 265-275, 2002
762002
Refactoring for data locality
K Beyls, EH D'Hollander
Computer 42 (2), 62-71, 2009
752009
Estimation of the pore size distribution from the moisture characteristic
EH d'Hollander
Water Resources Research 15 (1), 107-112, 1979
731979
Performance modeling for FPGAs: extending the roofline model with high-level synthesis tools
B Da Silva, A Braeken, EH D’Hollander, A Touhafi
International Journal of Reconfigurable Computing 2013, 2013
612013
Partitioning and labeling of index sets in do loops with constant dependence vectors
E D'HOLLANDER
1989 International Conference on Parallel Processing, University Park, PA, 1989
441989
Spike recognition and on-line classification by unsupervised learning system
EH D'Hollander, GA Orban
IEEE Transactions on Biomedical Engineering, 279-284, 1979
411979
Visualizing the impact of the cache on program execution
Y Yu, K Beyls, EH D'Hollander
Proceedings Fifth International Conference on Information Visualisation, 336-341, 2001
402001
Finding and applying loop transformations for generating optimized FPGA implementations
H Devos, K Beyls, M Christiaens, JV Campenhout, EH D’Hollander, ...
Transactions on High-Performance Embedded Architectures and Compilers I, 159-178, 2007
382007
Loop parallelization using the 3D iteration space visualizer
Y Yu, EH D'HOLLANDER
Journal of visual languages & computing 12 (2), 163-181, 2001
322001
Software refactoring guided by multiple soft-goals
Y Yu, J Mylopoulos, J Leite, L Liu, EH D'Hollander
312003
Comparing and combining GPU and FPGA accelerators in an image processing context
B Da Silva, A Braeken, EH D'Hollander, A Touhafi, JG Cornelis, J Lemeire
2013 23rd International Conference on Field programmable Logic and …, 2013
262013
Compile-time cache hint generation for EPIC architectures
K Beyls, E D’Hollander
2nd Workshop on Explicitly Parallel Instruction Computing Architecture and …, 2002
252002
Intermediately executed code is the key to find refactorings that improve temporal data locality
K Beyls, EH D'Hollander
Proceedings of the 3rd Conference on Computing Frontiers, 373-382, 2006
232006
Platform-independent cache optimization by pinpointing low-locality reuse
K Beyls, EH D’Hollander
International Conference On Computational Science, 448-455, 2004
222004
The fortran parallel transformer and its programming environment
EH D'Hollander, F Zhang, Q Wang
Information sciences 106 (3-4), 293-317, 1998
181998
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