| A 7 ps Jitter 0.053 mm Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC D Shin, J Song, H Chae, C Kim IEEE journal of solid-state circuits 44 (9), 2437-2451, 2009 | 76 | 2009 |
| 8.1 a 224Gb/s DAC-based PAM-4 transmitter with 8-tap FFE in 10nm CMOS J Kim, S Kundu, A Balankutty, M Beach, BC Kim, S Kim, Y Liu, SK Murthy, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 126-128, 2021 | 56 | 2021 |
| A 3.57 Gb/s/pin low jitter all-digital DLL with dual DCC circuit for GDDR3 DRAM in 54-nm CMOS technology WJ Yun, HW Lee, D Shin, S Kim IEEE transactions on very large scale integration (VLSI) systems 19 (9 …, 2010 | 42 | 2010 |
| A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology WJ Yun, HW Lee, D Shin, SD Kang, JY Yang, HO Lee, DU Lee, S Sim, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 41 | 2008 |
| 2.8 a mixed-mode injection frequency-locked loop for self-calibration of injection locking range and phase noise in 0.13 µm CMOS D Shin, S Raman, KJ Koh 2016 IEEE International Solid-State Circuits Conference (ISSCC), 50-51, 2016 | 38 | 2016 |
| DLL circuit and method of controlling the same DS Shin, H Lee, WJ Yun US Patent 7,598,783, 2009 | 37 | 2009 |
| A 224-Gb/s DAC-based PAM-4 quarter-rate transmitter with 8-tap FFE in 10-nm FinFET J Kim, S Kundu, A Balankutty, M Beach, BC Kim, ST Kim, Y Liu, SK Murthy, ... IEEE Journal of Solid-State Circuits 57 (1), 6-20, 2021 | 30 | 2021 |
| An injection frequency-locked loop—Autonomous injection frequency tracking loop with phase noise self-calibration for power-efficient mm-wave signal sources D Shin, KJ Koh IEEE Journal of Solid-State Circuits 53 (3), 825-838, 2018 | 30 | 2018 |
| Duty detection circuit and duty cycle correction circuit including the same DS Shin US Patent 8,207,772, 2012 | 24 | 2012 |
| Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface D Shin, KJ Na, D Kwon, JH Kang, T Song, HD Jung, WY Lee, KC Park, ... 2009 Symposium on VLSI Circuits, 138-139, 2009 | 24 | 2009 |
| 24-GHz injection-locked frequency tripler with third-harmonic quadrature phase generator D Shin, KJ Koh IEEE Transactions on Circuits and Systems I: Regular Papers 66 (8), 2898-2906, 2019 | 21 | 2019 |
| Duty detecting circuit and duty cycle corrector including the same DS Shin US Patent 7,847,609, 2010 | 20 | 2010 |
| A 7ps-jitter 0.053 mm2 fast-lock addll with wide-range and high-resolution all-digital dcc D Shin, J Song, H Chae, KW Kim, YJ Choi, C Kim 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 17 | 2007 |
| Power-down mode control apparatus and DLL circuit having the same H Lee, WJ Yun, DS Shin US Patent 7,683,684, 2010 | 16 | 2010 |
| A low-jitter open-loop all-digital clock generator with two-cycle lock-time MY Kim, D Shin, H Chae, C Kim IEEE transactions on very large scale integration (VLSI) systems 17 (10 …, 2009 | 16 | 2009 |
| Impedance-controlled pseudo-open drain output driver circuit and method for driving the same DS Shin, I Jung, C Kim, HD Lee, YJ Choi US Patent 7,579,861, 2009 | 15 | 2009 |
| Open-loop slew-rate controlled output driver DS Shin, IH Jung, J Kim, C Kim, HD Lee US Patent 7,449,936, 2008 | 14 | 2008 |
| A 0.17–1.4 GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme D Shin, WJ Yun, HW Lee, YJ Choi, S Kim, C Kim ESSCIRC 2008-34th European Solid-State Circuits Conference, 82-85, 2008 | 13 | 2008 |
| DLL circuit and method of controlling the same DS Shin US Patent 7,737,746, 2010 | 12 | 2010 |
| 11.5 A 23.9-to-29.4 GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET D Shin, HS Kim, C Liu, P Wali, SK Murthy, Y Fan 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 188-190, 2021 | 11 | 2021 |
