| 3-D topologies for networks-on-chip VF Pavlidis, EG Friedman Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 15 (10 …, 2007 | 535 | 2007 |
| Three-dimensional integrated circuit design VF Pavlidis, EG Friedman Morgan Kaufmann Pub, 2009 | 371* | 2009 |
| Three-dimensional integrated circuits VF Pavlidis, EG Friedman Burlington, MA: Morgan Kaufmann, 2009 | 368* | 2009 |
| Interconnect-based design methodologies for three-dimensional integrated circuits VF Pavlidis, EG Friedman Proceedings of the IEEE 97 (1), 123-140, 2009 | 135 | 2009 |
| Performance analysis of 3-D monolithic integrated circuits S Bobba, A Chakraborty, O Thomas, P Batude, VF Pavlidis, G De Micheli 2010 IEEE International 3D Systems Integration Conference (3DIC), 1-4, 2010 | 129 | 2010 |
| Clock distribution networks for 3-D integrated Circuits VF Pavlidis, I Savidis, EG Friedman Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, 651-654, 2008 | 74 | 2008 |
| Clock distribution networks in 3-D integrated systems VF Pavlidis, I Savidis, EG Friedman IEEE Transactions on very large scale integration (VLSI) systems 19 (12 …, 2011 | 52 | 2011 |
| Analytical heat transfer model for thermal through-silicon vias H Xu, VF Pavlidis, G De Micheli Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, 1-6, 2011 | 41 | 2011 |
| Interconnect delay minimization through interlayer via placement in 3-D ICs VF Pavlidis, EG Friedman Proceedings of the 15th ACM Great Lakes symposium on VLSI, 20-25, 2005 | 36 | 2005 |
| A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric K Siozios, VF Pavlidis, D Soudris ACM Transactions on Reconfigurable Technology and Systems (TRETS) 5 (1), 4, 2012 | 26 | 2012 |
| Power distribution paths in 3-D ICS VF Pavlidis, G De Micheli Proceedings of the 19th ACM Great Lakes symposium on VLSI, 263-268, 2009 | 24 | 2009 |
| The combined effect of process variations and power supply noise on clock skew and jitter H Xu, VF Pavlidis, W Burleson, G De Micheli Quality Electronic Design (ISQED), 2012 13th International Symposium on, 320-327, 2012 | 19 | 2012 |
| A software-supported methodology for designing high-performance 3D FPGA architectures K Siozios, K Sotiriadis, VF Pavlidis, D Soudris 2007 IFIP International Conference on Very Large Scale Integration, 54-59, 2007 | 19 | 2007 |
| Effect of process variations in 3D global clock distribution networks H Xu, VF Pavlidis, G De Micheli ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (3), 20, 2012 | 16 | 2012 |
| Exploring alternative 3D FPGA architectures: design methodology and CAD tool support K Siozios, K Sotiriadis, VF Pavlidis, D Soudris Field Programmable Logic and Applications, 2007. FPL 2007. International …, 2007 | 16 | 2007 |
| Via placement for minimum interconnect delay in three-dimensional (3D) circuits VF Pavlidis, EG Friedman 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-4590, 2006 | 16 | 2006 |
| Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs IA Papistas, VF Pavlidis 2015 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2015 | 14 | 2015 |
| Designing low-power energy recovery adders based on pass transistor logic D Soudris, V Pavlidis, A Thanailakis ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and …, 2001 | 13 | 2001 |
| Interconnect design tradeoffs for silicon and glass interposers H Kalargaris, VF Pavlidis 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 77-80, 2014 | 12 | 2014 |
| Timing uncertainty in 3-D clock trees due to process variations and power supply noise H Xu, VF Pavlidis, X Tang, W Burleson, G De Micheli IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (12 …, 2013 | 12 | 2013 |
Eby G. FriedmanDistinguished Professor, University of RochesterVerified email at ece.rochester.edu
