| A 1.0 V, 2.5 mW, transformer noise-canceling UWB CMOS LNA T Kihara, T Matsuoka, K Taniguchi 2008 IEEE Radio Frequency Integrated Circuits Symposium, 493-496, 2008 | 26 | 2008 |
| Semiconductor device M Mizokami, T Kihara US Patent 10,305,533, 2019 | 25 | 2019 |
| A multiband LTE SAW-less CMOS transmitter with source-follower-driven passive mixers, envelope-tracked RF-PGAs, and marchand baluns T Kihara, T Sano, M Mizokami, Y Furuta, M Hokazono, T Maruyama, ... IEICE transactions on electronics 96 (6), 774-782, 2013 | 22 | 2013 |
| Analytical design of a 0.5 V 5GHz CMOS LC-VCO F Yamashita, T Matsuoka, T Kihara, I Takobe, HJ Park, K Taniguchi IEICE Electronics Express 6 (14), 1025-1031, 2009 | 20 | 2009 |
| Digital mismatch correction for bandpass sampling four-channel time-interleaved ADCs in direct-RF sampling receivers T Kihara, T Takahashi, T Yoshimura IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2007-2016, 2019 | 18 | 2019 |
| Small-signal and noise model of fully depleted silicon-on-insulator metal–oxide–semiconductor devices for low-noise amplifier G Kim, B Murakami, M Goto, T Kihara, K Nakamura, Y Shimizu, ... Japanese journal of applied physics 45 (9R), 6872, 2006 | 17 | 2006 |
| A low-voltage design of controller-based ADPLL for implantable biomedical devices J Bae, S Radhapuram, I Jo, T Kihara, T Matsuoka 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2015 | 15 | 2015 |
| Low-voltage wireless analog CMOS circuits toward 0.5 V operation T Matsuoka, J Wang, T Kihara, H Ham, K Taniguchi IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2010 | 12 | 2010 |
| A 0.55 V back-gate controlled ring VCO for ADCs in 65 nm SOTB CMOS T Yoshio, T Kihara, T Yoshimura 2017 IEEE Asia Pacific microwave conference (APMC), 946-948, 2017 | 11 | 2017 |
| Semiconductor device and adjustment method of filter circuit T Kihara, T Sano US Patent 9,190,977, 2015 | 10 | 2015 |
| A 0.5 V area-efficient transformer folded-cascode low-noise amplifier in 90 nm CMOS T Kihara, HJ Park, I Takobe, F Yamashita, T Matsuoka, K Taniguchi 2008 IEEE International Conference on Integrated Circuit Design and …, 2008 | 9 | 2008 |
| A design of 0.7-V 400-MHz all-digital phase-locked loop for implantable biomedical devices J Bae, S Radhapuram, I Jo, W Wang, T Kihara, T Matsuoka IEICE Transactions on Electronics 99 (4), 431-439, 2016 | 8 | 2016 |
| A subthreshold low-voltage low-phase-noise CMOS LC-VCO with resistive biasing J Bae, S Radhapuram, I Jo, T Kihara, T Matsuoka Circuits and Systems 6 (5), 136-142, 2015 | 8 | 2015 |
| Quadrature modulator and semiconductor integrated circuit with it built-in T Nakamura, T Yamawaki, T Norimatsu, T Kihara US Patent 8,299,865, 2012 | 7 | 2012 |
| A 0.5 V area-efficient transformer folded-cascode CMOS low-noise amplifier T Kihara, HJ Park, I Takobe, F Yamashita, T Matsuoka, K Taniguchi IEICE transactions on electronics 92 (4), 564-575, 2009 | 7 | 2009 |
| Spur reduction by self-injection loop in a fractional-N PLL M Kobayashi, Y Masui, T Kihara, T Yoshimura 2017 24th IEEE International Conference on Electronics, Circuits and Systems …, 2017 | 6 | 2017 |
| Analysis and design of differential LNAs with on-chip transformers in 65-nm CMOS technology T Kihara, S Matsuda, T Yoshimura 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2016 | 6 | 2016 |
| A design of 0.7-V 400-MHz digitally-controlled oscillator J Bae, S Radhapuram, I Jo, T Kihara, T Matsuoka IEICE Transactions on Electronics 98 (12), 1179-1186, 2015 | 6 | 2015 |
| Semiconductor device T Kihara US Patent 8,941,213, 2015 | 6 | 2015 |
| A low-power CMOS programmable frequency divider with novel retiming scheme S Radhapuram, J Bae, I Jo, T Kihara, T Matsuoka IEICE Electronics Express 12 (6), 20141233-20141233, 2015 | 6 | 2015 |
Toshimasa MatsuokaAssociate Professor, Osaka University確認したメール アドレス: eei.eng.osaka-u.ac.jp
